1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device and write data masking method thereof for preventing unwanted data from being written into memory cells.
2. Description of the Related Art
The SDRAM (Synchronous DRAM) works according to externally applied clock signals and has a higher data transfer rate compared to the asynchronous DRAM. Hence, the development of the SDRAM effectively contributes to improving the operational speed of a computer system. The conventional SDRAM can transfer only a single set of data in a single clock cycle on either the rising or falling edge of the externally applied clock signal. Such conventional data transfer approaches are generally not compatible with the increasing demand for higher operational speed.
In order to resolve such problems there exists another kind of SDRAM that performs the data input and output operations at both the rising and falling edges of a data strobe signal whose period is the same as that of the clock signal in data read and write operations. This device can therefore perform two data input and output operations in one clock period, and is therefore commonly referred to as a double data rate (DDR) SDRAM. Namely, the DDR SDRAM has double the data transfer rate of the conventional SDRAM, which makes it relatively suited for use in advanced computer systems.
The DDR SDRAM is different from the conventional SDRAM in the construction of the memory cell array and in the data access method it uses. In particular, in the DDR SDRAM, the memory cell array block consists of an even numbered memory cell array block and an odd numbered memory cell array block. The memory cells of the even numbered memory cell array block are accessed by even numbered column selection signals generated by an even numbered column decoder. Similarly, the memory cells of the odd numbered memory cell array block are accessed by the odd numbered column selection signals generated by an odd numbered column decoder. Hence, the DDR SDRAM inputs two sets of data in one clock cycle in response to the data strobe signal, and the two sets of data are simultaneously written into the memory cells of the even and odd numbered memory cell array blocks, which are simultaneously accessed by even and odd numbered column selection signals, respectively, generated by the even and odd numbered column decoders.
The DDR SDRAM has a write data masking function for preventing unwanted data from being written into the even and/or odd numbered memory cell arrays. The masking control signals are supplied through two pins provided in the DDR SDRAM. Furthermore, the conventional DDR SDRAM is designed such that the even numbered data may be written only into the even numbered memory cell array block, and the odd numbered data only into the odd numbered memory cell array block. That is, the even numbered data may not be written into the odd numbered memory cell array block, and the odd numbered data may not be written into the even numbered memory cell array block.